Research Engineer, Physical Design, RAM / Cell Design, Low Power, Future CMOS
Cambridge to £ High High Calibre Semiconductor Engineer to work on future generation CMOS research. An unusual opportunity for a talented academic or post grad experienced Physical Designer to join a world leading highly motivated successful research group with an excellent track record in ground breaking research. The successful candidate will be involved in a team working with universities and other research centres focused on the areas of low power design, variability, wearout analysis and mitigation on sub 45nm technologies. The environment in the research group allows experimentation and provides autonomy, but expects innovation and results; hence the successful candidate will be of a very high calibre. You must have a strong background in physical design and implementation and should have an exceptional qualification in Electronic Engineering or Computer Science/Engineering or a related discipline with post graduation experience in implementation and physical design. You should also have a wide understanding of design techniques from circuits through to RTL, and be able to demonstrate detailed knowledge of at least one of the following areas: EDA flows - implementation and physical design, RAM and standard cell design, current and future CMOS processes and DFM issues Dynamic and leakage power reduction techniques. ARM/RISC microprocessor architecture, system level design and system on chip architecture would be a big advantage.